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datasheet 9fgv0631c october 18, 2016 1 ?2016 integrated device technology, inc. 6-o/p 1.8v pcie gen 1-2-3 clock generator 9fgv0631c general description the 9fgv0631c is a member of idt's soc-friendly 1.8v very-low-power pcie clock family. the device has 6 output enables for clock management, 2 different spread spectrum levels in addition to spread off and 2 selectable smbus addresses. recommended application 1.8v pcie gen 1-2-3 clock generator output features ? 6 - 100mhz low-power (lp) hcsl dif pairs ? 1 - 1.8v lvcmos ref output w/wake-on-lan (wol) support key specifications ? dif cycle-to-cycle jitter <50ps ? dif output-to-output skew <50ps ? dif phase jitter is pcie gen1-2-3 compliant ? ref phase jitter is <1.5ps rms features/benefits ? lp-hcsl outputs; save 12 resistors compared to standard pcie devices ? 54mw typical power consum ption; reduced thermal concerns ? outputs can optionally be supplied from any voltage between 1.05v and 1.8v; maximum power savings ? oe# pins; support dif power management ? programmable slew rate for each output; allows tuning for various line lengths ? programmable output amplitude; allows tuning for various application environments ? dif outputs blocked until pll is locked; clean system start-up ? selectable 0%, -0.25% or -0.5% spread on dif outputs; reduces emi ? external 25mhz crystal; supports tight ppm with 0 ppm synthesis error ? configuration can be accomplished with strapping pins; smbus interface not required for device control ? 3.3v tolerant smbus interface works with legacy controllers ? selectable smbus addresses; mu ltiple devices can easily share an smbus segment ? space saving 40-pin 5x5 mm vfqfpn; minimal board space block diagram xin/clkin_25 x2 control logic vss_en_tri ^ckpwrgd_pd# sdata_3.3 ss capable pll osc ref1.8 voe(5:0)# sclk_3.3 vsadr dif5 dif4 dif3 dif2 dif1 dif0
6-o/p 1.8v pcie gen 1-2-3 clock generator 2 october 18, 2016 9fgv0631c datasheet pin configuration smbus address selection table power management table power connections ^ckpwrgd_pd# vddio voe5# dif5# dif5 voe4# dif4# dif4 vddio vdd1.8 40 39 38 37 36 35 34 33 32 31 vss_en_tri 130 voe3# x1_25 229 dif3# x2 328 dif3 vddxtal1.8 427 vddio vddref1.8 526 vdda1.8 vsadr/ref1.8 625 nc nc 724 voe2# gnddig 823 dif2# sclk_3.3 922 dif2 sdata_3.3 10 21 voe1# 11 12 13 14 15 16 17 18 19 20 vdddig1.8 vddio voe0# dif0 dif0# vdd1.8 vddio dif1 dif1# nc v prefix indicates internal 120kohm pull down resistor ^ prefix indicates internal 120kohm pull up resistor 9fgv0631c paddle is gnd 40-pin vfqfpn, 5x5 mm, 0.4mm pitch sadr address 0 1101000 1 1101010 x x state of sadr on first application of ckpwrgd_pd# + read/write bit oex# true o/p comp. o/p 0 x x low low hi-z 1 1 1 0 running running running 1 0 1 low low low ref ckpwrgd_pd# smbus oe bit difx 1. ref is hi-z until the 1st assertion of ckpwrgd_pd# high. after this, when ckpwrg_pd# is low, ref is low. pin number vdd vddio gnd 441xtal osc 5 41 ref power 11 8 digital (dirty) power 12,17,27,32,39 41 dif outputs 26 41 pll analog description
october 18, 2016 3 6-o/p 1.8v pc ie gen 1-2-3 clock generator 9fgv0631c datasheet pin descriptions pin # pin name pin type description 1 vss_en_tri latched in latched select input to select spread spectrum amount at initial power up : 1 = -0.5% spread, m = -0.25%, 0 = spread off 2 x1_25 in crystal input, nominally 25.00mhz. 3 x2 out crystal output. 4 vddxtal1.8 pwr power supply for xtal, nominal 1.8v 5 vddref1.8 pwr vdd for ref output. nominal 1.8v. 6 vsadr/ref1.8 latched i/o latch to select smbus address/1.8v lvcmos copy of x1/refin pin 7 nc n/a no connection. 8 gnddig gnd ground pin for digital circuitry 9 sclk_3.3 in clock pin of smbus circuitry, 3.3v tolerant. 10 sdata_3.3 i/o data pin for smbus circuitry, 3.3v tolerant. 11 vdddig1.8 pwr 1.8v digital power (dirty power) 12 vddio pwr power supply for differential outputs 13 voe0# in active low input for enabling dif pair 0. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 14 dif0 out differential true clock output 15 dif0# out differential complementary clock output 16 vdd1.8 pwr power supply, nominal 1.8v 17 vddio pwr power supply for differential outputs 18 dif1 out differential true clock output 19 dif1# out differential complementary clock output 20 nc n/a no connection. 21 voe1# in active low input for enabling dif pair 1. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 22 dif2 out differential true clock output 23 dif2# out differential complementary clock output 24 voe2# in active low input for enabling dif pair 2. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 25 nc n/a no connection. 26 vdda1.8 pwr 1.8v power for the pll core. 27 vddio pwr power supply for differential outputs 28 dif3 out differential true clock output 29 dif3# out differential complementary clock output 30 voe3# in active low input for enabling dif pair 3. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 31 vdd1.8 pwr power supply, nominal 1.8v 32 vddio pwr power supply for differential outputs 33 dif4 out differential true clock output 34 dif4# out differential complementary clock output 35 voe4# in active low input for enabling dif pair 4. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 36 dif5 out differential true clock output 37 dif5# out differential complementary clock output 38 voe5# in active low input for enabling dif pair 5. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 39 vddio pwr power supply for differential outputs 40 ^ckpwrgd_pd# in input notifies device to sample latched inputs and start up on first high assertion. low enters power down mode, subsequent high assertions exit power down mode. this pin has internal pull-up resistor. 41 epad gnd connect paddle to ground.
6-o/p 1.8v pcie gen 1-2-3 clock generator 4 october 18, 2016 9fgv0631c datasheet test loads alternate differential output terminations rs zo units 33 100 27 85 ohms ref output 33 ref output test load 5pf zo = 50 ohms rs rs low-power differential output test load 2pf 2pf 5 inches zo=100 ohms lvds clk input l4 r8b r7b r8a r7a 3.3 volts cc cc rs rs driving lvds driving lvds inputs receiver has termination receiver does not have termination r7a, r7b 10k ohm 140 ohm r8a, r8b 5.6k ohm 75 ohm cc 0.1 uf 0.1 uf vcm 1.2 volts 1.2 volts component value note
october 18, 2016 5 6-o/p 1.8v pc ie gen 1-2-3 clock generator 9fgv0631c datasheet absolute maximum ratings stresses above the ratings lis ted below can cause permanent damage to the 9fgv0631c. these ratings, which are standard values for idt commercially rated parts, are stress ratings on ly. functional operation of the device at these or any other conditions above those indicated in the operational sections of th e specifications is not implied. exposure to absolute maximum rating conditions for extended periods ca n affect product reliability. electrical parameters are guaranteed only over the recommended operating temperature range. electrical characteristi cs?current consumption electrical characteristics?dif output duty cycle, jitter, and sk ew characteristics parameter symbol conditions min typ max units notes supply voltage vddxx applies to all vdd pins -0.5 2.5 v 1,2 input voltage v in -0.5 v dd +0.5v v 1, 3 input high voltage, smbus v ihsmb smbus clock and data pins 3.6v v 1 storage temperature ts -65 150 c 1 junction temperature tj 125 c 1 input esd protection esd prot human body model 2000 v 1 1 guaranteed by design and characterization, not 100% tested in production. 2 operation under these conditions is neither implied nor guaranteed. 3 not to exceed 2.5v. ta = t amb; supply voltages per normal operation conditions, see test loads for loading conditions parameter symbol conditions min typ max units notes i ddaop vdda, all outputs active @100mhz 6.1 9 ma i ddop all vdd, except vdda and vddio, all outputs active @100mhz 10.5 15 ma i ddi oop vddio, all outputs active @100mhz 22 30 ma i ddap d vdda, dif outputs off, ref output running 0.4 1 ma 2 i ddpd all vdd, except vdda and vddio, dif outputs off, ref output running 5.5 8 ma 2 i ddi opd vddio, dif outputs off, ref output running 0.04 0.1 ma 2 i ddap d vdda, all outputs off 0.4 1 ma i ddpd all vdd, except vdda and vddio, all outputs off 0.6 1 ma i ddi opd vddio, all outputs off 0.0003 0.1 ma 1 guaranteed by design and characterization, not 100% tested in production. 2 this is the current required to have the ref output runnin g in wake-on-lan mode (byte 3, bit 5 = 1) operating supply current wake-on-lan current (ckpwrgd_pd# = '0' byte 3, bit 5 = '1') powerdown current (ckpwrgd_pd# = '0' byte 3, bit 5 = '0') ta = t amb; supply voltages per normal operation conditions, see test loads for loading conditions parameter symbol conditions min typ max units notes duty cycle t d c measured differentially, pll mode 45 49.9 55 % 1,2 skew, output to output t sk3 averaging on, v t = 50% 3750ps1,2 jitter, cycle to cycle t jcyc-cyc 12 50 ps 1,2 1 guaranteed by desi g n and characterization, not 100% tested in production. 2 measured from differential waveform
6-o/p 1.8v pcie gen 1-2-3 clock generator 6 october 18, 2016 9fgv0631c datasheet electrical characteristics?input/supp ly/common output parameters?normal operating conditions ta = t amb; supply voltages per normal operation conditions, see test loads for loading conditions parameter symbol conditions min typ max units notes supply voltage vddxx supply voltage for core, analog and single-ended lvcmos outputs 1.7 1.8 1.9 v output supply voltage vddio supply voltage for differential low power outputs 0.9975 1.05-1.8 1.9 v commmercial r ange 0 25 70 c industrial range -40 25 85 c input high voltage v ih single-ended inputs, except smbus 0.75 v dd v dd + 0.3 v input mid voltage v im single-ended tri-level inputs ('_tri' suffix) 0.4 v dd 0.5 v dd 0.6 v dd v input low voltage v il single-ended inputs, except smbus -0.3 0.25 v dd v output high voltage v ih single-ended outputs, except smbus. i oh = -2ma v dd -0.45 v output low voltage v il single-ended outputs, except smbus. i ol = -2ma 0.45 v i in single-ended inputs, v in = gnd, v in = vdd -5 5 ua i inp single-ended inputs v in = 0 v; inputs with internal pull-up resistors v in = vdd; inputs with internal pull-down resistors -200 200 ua input frequency f in xtal, or x1 input 23 25 27 mhz pin inductance l p in 7nh1 c in logic inputs, except dif_in 1.5 5 pf 1 c ou t output pin capacitance 6 pf 1 clk stabilization t stab from v dd power-up and after input clock stabilization or de-assertion of pd# to 1st clock 0.6 1.8 ms 1,2 ss modulation frequency f mod allowable frequency (triangular modulation) 30 31.6 33 khz 1 oe# latency t latoe# dif start after oe# assertion dif stop after oe# deassertion 1 3 3 clocks 1,3 tdrive_pd# t drvpd dif output enable after pd# de-assertion 20 300 us 1,3 tfall t f fall time of single-ended control inputs 5 ns 2 trise t r rise time of single-ended control inputs 5 ns 2 smbus input low voltage v ilsmb v ddsmb = 3.3v, see note 4 for v ddsmb < 3.3v 0.6 v smbus input high voltage v ihsmb v ddsmb = 3.3v, see note 5 for v ddsmb < 3.3v 2.1 3.6 v 4 smbus output low voltage v olsmb @ i pullup 0.4 v smbus sink current i pullup @ v ol 4ma nominal bus voltage v ddsmb 1.7 3.6 v sclk/sdata rise time t rsmb (max vil - 0.15) to (min vih + 0.15) 1000 ns 1 sclk/sdata fall time t fsmb (min vih + 0.15) to (max vil - 0.15) 300 ns 1 smbus operating frequency f maxsmb maximum smbus operating frequency 400 khz 1 1 guaranteed by design and characterization, not 100% tested in production. 2 control input must be monotonic from 20% to 80% of input swing. capacitance 3 time from deassertion until out p uts are >200 mv 4 for v ddsmb < 3.3v, v ihsmb >= 0.65xv ddsmb input current ambient operating temperature t amb
october 18, 2016 7 6-o/p 1.8v pc ie gen 1-2-3 clock generator 9fgv0631c datasheet electrical characteristics?di f low power hcsl outputs electrical characteristics?dif output phase jitter parameters ta = t amb; supply voltages per normal operation conditions, see test loads for loading conditions parameter symbol conditions min typ max units notes scope avera g in g on fast settin g 1.8 2.7 4.4 v/ns 1,2,3 scope averaging on slow setting 1.4 2.1 3.4 v/ns 1,2,3 slew rate matchin g trf slew rate matchin g , scope avera g in g on 4 20 % 1,2,4 voltage high v hi gh 660 793 850 7 voltage low v low -150 16 150 7 max voltage vmax 831 1150 7 min volta g e vmin -300 -95 7 vswin g vswin g scope avera g in g off 300 1555 mv 1,2,7 crossing voltage (abs) vcross_abs scope averaging off 250 429 550 mv 1,5,7 crossing voltage (var) -vcross scope averaging off 12 140 mv 1,6,7 2 measured from differential waveform 7 at default smbus amplitude settin g s. 1 guaranteed by design and characterization, not 100% tested in production. 3 slew rate is measured through the vswing voltage range centered around differential 0v. this results in a +/-150mv window arou nd differential 0v. 4 matching applies to rising edge rate for clock and falling edge rate for clock#. it is measured using a +/-75mv window centered on the average cross point where clock rising meets clock# falling. the median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. 5 vcross is defined as voltage where clock = clock# measured on a component test board and only applies to the differential risi ng edge (i.e. clock rising and clock# falling). 6 the total variation of all vcross measurements in any particular system. note that this is a subset of vcross_min/max (vcross absolute) allowed. the intent is to limit vcross induced modulation by setting -vcross to be smaller than vcross absolute. slew rate trf statistical measurement on single-ended signal using oscilloscope math function. (scope averaging on) mv measurement on single ended signal using absolute value. (scope avera g in g off) mv ta = t amb; supply voltages per normal operation conditions, see test loads for loading conditions parameter symbol conditions min typ max ind. limit units notes t jp hpcieg1 pcie gen 1 25 35 86 ps (p-p) 1,2,3 pcie gen 2 lo band 10khz < f < 1.5mhz 0.9 1.1 3 ps (rms) 1,2,3 pcie gen 2 high band 1.5mhz < f < nyquist (50mhz) 1.6 1.9 3.1 ps (rms) 1,2,3 t jphpcieg3 pcie gen 3 common clock architecture (pll bw of 2-4 or 2-5mhz, cdr = 10mhz) 0.36 0.5 1 ps (rms) 1,2,3 t jphpcieg3srn s pcie gen 3 separate reference no spread (srns) (pll bw of 2-4 or 2-5mhz, cdr = 10mhz) 0.36 0.5 0.7 ps (rms) 1,2,3 1 guaranteed by design and characterization, not 100% tested in production. 4 applies to all differential outputs phase jitter, pll mode 4 t jphpcieg2 2 see http://www.pcisig.com for complete specs 3 sample size of at least 100k cycles. this figures extrapolates to 108ps pk-pk @ 1m cycles for a ber of 1-12.
6-o/p 1.8v pcie gen 1-2-3 clock generator 8 october 18, 2016 9fgv0631c datasheet electrical characteristics?ref clock periods?differential outputs with spread spectrum disabled clock periods?differential outputs with spread spectrum enabled clock periods?single-ended outputs ta = t amb; supply voltages per normal operation conditions, see test loads for loading conditions parameter symbo l conditions min typ max units notes long accuracy ppm see tperiod min-max values ppm 1,2 clock period t p eriod 25 mhz output 40 ns 2 rise/fall slew rate t rf1 byte 3 = 1f, 20% to 80% of vddref 0.6 1 1.6 v/ns 1 rise/fall slew rate t rf1 byte 3 = 5f, 20% to 80% of vddref 0.9 1.4 2.2 v/ns 1,3 rise/fall slew rate t rf1 byte 3 = 9f, 20% to 80% of vddref 1.1 1.7 2.7 v/ns 1 rise/fall slew rate t rf1 byte 3 = df, 20% to 80% of vddref 1.1 1.8 2.9 v/ns 1 duty cycle d t1x v t = vdd/2 v 45 49.1 55 % 1,4 duty cycle distortion d tcd v t = vdd/2 v 0 2 4 % 1,5 jitter, cycle to cycle t j c y c-c y c v t = vdd/2 v 19.1 250 ps 1,4 noise floor t j dbc1k 1khz offset -129.8 -105 dbc 1,4 noise floor t j dbc10k 10khz offset to nyquist -143.6 -115 dbc 1,4 jitter, phase t jphref 12khz to 5mhz 0.63 1.5 ps (rms) 1,4 1 guaranteed by design and characterization, not 100% tested in production. 3 default smbus value 4 when driven by a crystal. 5 when driven by an external oscillator via the x1 pin, x2 should be floating. 2 all lon g term accuracy and clock period specifications are g uaranteed assumin g that ref is trimmed to 25.00 mhz 0 1 clock 1us 0.1s 0.1s 0.1s 1us 1 clock -c2c jitter absper min -ssc short-term average min - ppm long-term average min 0 ppm period nominal + ppm long-term average ma x +ssc short-term average ma x +c2c jitter absper max dif 100.00 9.94900 9.99900 10.00000 10.00100 10.05100 ns 1,2 measurement wi ndow units ssc off center freq. mhz notes 1 clock 1us 0.1s 0.1s 0.1s 1us 1 clock -c2c jitter absper min -ssc short-term average min - ppm long-term average min 0 ppm period nominal + ppm long-term average ma x +ssc short-term average ma x +c2c jitter absper max dif 99.75 9.94906 9.99906 10.02406 10.02506 10.02607 10.05107 10.10107 ns 1,2 1 guaranteed by design and characterization, not 100% tested in production. 2 all long term accuracy specifications are guaranteed with the assumption that the crystal input is tuned to exactly 14.31818mhz . measurement wi ndow units ssc on center freq. mhz notes 1 clock 1us 0.1s 0.1s 0.1s 1us 1 clock -c2c jitter absper min -ssc short-term average min - ppm long-term average min 0 ppm period nominal + ppm long-term average max +ssc short-term average max +c2c jitter absper max ref 25.000 39.79880 39.99880 40.00000 40.00120 40.20120 ns 1,2 notes ssc off center freq. mhz measurement wi ndow units
october 18, 2016 9 6-o/p 1.8v pc ie gen 1-2-3 clock generator 9fgv0631c datasheet general smbus serial interface information how to write ? controller (host) sends a start bit ? controller (host) sends the write address ? idt clock will acknowledge ? controller (host) sends the beginning byte location = n ? idt clock will acknowledge ? controller (host) sends the byte count = x ? idt clock will acknowledge ? controller (host) starts sending byte n through byte n+x-1 ? idt clock will acknowledg e each byte one at a time ? controller (host) sends a stop bit note: read/write address is latched on sadr pin. how to read ? controller (host) will send a start bit ? controller (host) sends the write address ? idt clock will acknowledge ? controller (host) sends the beginning byte location = n ? idt clock will acknowledge ? controller (host) will send a separate start bit ? controller (host) sends the read address ? idt clock will acknowledge ? idt clock will send the data byte count = x ? idt clock sends byte n+x-1 ? idt clock sends byte 0 through byte x (if x (h) was written to byte 8) ? controller (host) will need to acknowledge each byte ? controller (host) will send a not acknowledge bit ? controller (host) will send a stop bit index block write operation controller (host) idt (slave/receiver) tstart bit slave address wr write ack beginning byte = n ack data byte count = x ack beginning byte n x byte ack o oo oo o byte n + x - 1 ack pstop bit index block read operation controller (host) idt (slave/receiver) tstart bit slave address wr write ack beginning byte = n ack rt repeat start slave address rd read ack data byte count=x ack x byte beginning byte n ack o oo oo o byte n + x - 1 n not acknowledge pstop bit
6-o/p 1.8v pcie gen 1-2-3 clock generator 10 october 18, 2016 9fgv0631c datasheet smbus table: output enable register 1 byte 0 name control function type 0 1 default bit 7 dif oe5 output enable rw low/low enabled 1 bit 6 dif oe4 output enable rw low/low enabled 1 bit 5 1 bit 4 dif oe3 output enable rw low/low enabled 1 bit 3 dif oe2 output enable rw low/low enabled 1 bit 2 dif oe1 output enable rw low/low enabled 1 bit 1 1 bit 0 dif oe0 output enable rw low/low enabled 1 1. a low on these bits will overide the oe# pin and force the differential output low/low smbus table: ss readback and control register byte 1 name control function type 0 1 default bit 7 ssenrb1 ss enable readback bit1 r latch bit 6 ssenrb1 ss enable readback bit0 r latch bit 5 ssen_swcntrl enable sw control of ss rw values in b1[7:6] control ss amount values in b1[4:3] control ss amount. 0 bit 4 ssensw1 ss enable software ctl bit1 rw 1 0 bit 3 ssensw0 ss enable software ctl bit0 rw 1 0 bit 2 1 bit 1 amplitude 1 rw 00 = 0.6v 01 = 0.7v 1 bit 0 amplitude 0 rw 10= 0.8v 11 = 0.9v 0 1. b1[5] must be set to a 1 for these bits to have any effect on the part. smbus table: dif slew rate control register byte 2 name control function type 0 1 default bit 7 slewratesel dif5 adjust slew rate of dif5 rw slow setting fast setting 1 bit 6 slewratesel dif4 adjust slew rate of dif4 rw slow setting fast setting 1 bit 5 1 bit 4 slewratesel dif3 adjust slew rate of dif3 rw slow setting fast setting 1 bit 3 slewratesel dif2 adjust slew rate of dif2 rw slow setting fast setting 1 bit 2 slewratesel dif1 adjust slew rate of dif1 rw slow setting fast setting 1 bit 1 1 bit 0 slewratesel dif0 adjust slew rate of dif0 rw slow setting fast setting 1 smbus table: nominal vhigh amplitude control/ ref control register byte 3 name control function type 0 1 default bit 7 rw 00 = slowest 01 = slow 0 bit 6 rw 10 = fast 11 = faster 1 bit 5 ref power down function wake-on-lan enable for ref rw ref does not run in power down ref runs in power down 0 bit 4 ref oe ref output enable rw low enabled 1 bit 3 1 bit 2 1 bit 1 1 bit 0 1 byte 4 is reserved reserved reserved reserved reserved 00' for ss_en_tri = 0, '01' for ss_en_tri = 'm', '11 for ss_en_tri = '1' 00' = ss off, '01' = -0.25% ss, '10' = reserved, '11'= -0.5% ss reserved controls output amplitude ref slew rate control reserved reserved reserved reserved
october 18, 2016 11 6-o/p 1.8v pc ie gen 1-2-3 clock generator 9fgv0631c datasheet recommended crystal char acteristics ( 3225 package) smbus table: revision and vendor id register byte 5 name control function type 0 1 default bit 7 rid3 r 0 bit 6 rid2 r 0 bit 5 rid1 r 0 bit 4 rid0 r 1 bit 3 vid3 r 0 bit 2 vid2 r 0 bit 1 vid1 r 0 bit 0 vid0 r 1 smbus table: device type/device id byte 6 name control function type 0 1 default bit 7 device type1 r 0 bit 6 device type0 r 0 bit 5 device id5 r 0 bit 4 device id4 r 0 bit 3 device id3 r 0 bit 2 device id2 r 1 bit 1 device id1 r 1 bit 0 device id0 r 0 smbus table: byte count register byte 7 name control function type 0 1 default bit 7 0 bit 6 0 bit 5 0 bit 4 bc4 rw 0 bit 3 bc3 rw 1 bit 2 bc2 rw 0 bit 1 bc1 rw 0 bit 0 bc0 rw 0 c rev = 0001 revision id writing to this register will configure how many bytes will be read back, default is = 8 bytes. vendor id byte count programming reserved 00 = fgx, 01 = dbx zdb/fob, 10 = dmx, 11= dbx fob reserved device type 000110 binary or 06 hex device id reserved 0001 = idt parameter value units notes frequency 25 mhz 1 resonance mode fundamental - 1 frequency tolerance @ 25c 20 ppm max 1 frequency stability, ref @ 25c over operating temperature range 20 ppm max 1 temperature range (commerical) 0~70 c 1 temperature range (industrial) -40~85 c 2 equivalent series resistance (esr) 50 ? 5 ppm max 1 notes: 1. fox 603-25-150. 2. for i-temp, fox 603-25-261.
6-o/p 1.8v pcie gen 1-2-3 clock generator 12 october 18, 2016 9fgv0631c datasheet thermal characteristics marking diagrams notes: 1. line 2: truncated part number. 2. ?i? denotes industrial temperature. 3. ?l? denotes rohs compliant package. 4. ?yyww? is the last two digits of the year and week that the part was assembled. 5. ?coo? denotes country of origin. 6. ?lot? is the lot number. parameter symbol conditions pkg typ. units notes jc junction to case 42 c/w 1 c/w 1 c/w 1 c/w 1 c/w 1 ja5 junction to air, 5 m/s air flow 27 c/w 1 thermal resistance ndg40 1 epad soldered to board ics v0631cil yyww coo lot ics gv0631cl yyww coo lot
october 18, 2016 13 6-o/p 1.8v pc ie gen 1-2-3 clock generator 9fgv0631c datasheet package outline and package dimensions (ndg40, 40-pin 5mm x 5mm vfqfpn) package dimensions are kept current with jedec publication no. 95 ordering information ?lf? suffix to the part number are the pb-free configuration and are rohs compliant. ?c? is the device revision designator (will not correlate with the datasheet revision). millimeters symbol min max a 0.80 1.00 a1 0 0.05 a3 0.20 reference b 0.18 0.30 e 0.40 basic n40 n d 10 n e 10 d x e basic 5.00 x 5.00 d2 3.55 3.80 e2 3.55 3.80 l 0.30 0.50 sawn singulation 1 2 n e d index area top view seating plane a3 a1 c a l e2 e2 2 d2 d2 2 e c 0.08 (ref) n d & n e odd (ref) n d & n e even (n d -1)x (ref) e n 1 2 b thermal base (typ) if n d & n e are even (n e -1)x (ref) e e 2 ep ? exposed thermal pad should be externally connected part / order number shipping packaging package temperature 9FGV0631CKLF trays 40-pin vfqfpn 0 to +70 c 9FGV0631CKLFt tape and reel 40-pin vfqfpn 0 to +70 c 9fgv0631ckilf trays 40-pin vfqfpn -40 to +85 c 9fgv0631ckilft tape and reel 40-pin vfqfpn -40 to +85 c
6-o/p 1.8v pcie gen 1-2-3 clock generator 14 october 18, 2016 9fgv0631c datasheet revision history rev. intiator issue date description page # a rdw 9/29/2014 1. updated front page text and block diagram. 2. updated pin out to remove references to vdd suspend pins. using the part with collapsible power supplies did not save power and complicated board design. no pins were changed. 3. updated smbus descriptions 4. simplified footnote 2 on ppm table. 5. updated all electrical tables 6. move to final various b rdw 10/18/2016 removed idt crystal part number
disclaimer integrated device technology, inc. (idt) and its subsidiaries reserve the right to modify the products and/or specifications d escribed herein at any time and at idt?s sole discretion. all information in this document, including descriptions of product features and performance, is subject to change without notice. performance spe cifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. the information co ntained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limi ted to, the suitab ility of idt?s products for any particular purpose, an implied war ranty of merchantability, or non-infringement of the intellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third pa rties. idt?s products are not intended for use in applications involvin g extreme environmental conditions or in life support systems o r similar devices where the failure or malfun ction of an idt product can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their o wn risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered trademarks of idt. product specification subject to change wi thout notice. other trademarks and service marks used herein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright ?2016 integrated device technology, inc.. all rights reserved. corporate headquarters 6024 silver creek valley road san jose, ca 95138 usa sales 1-800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com tech support email: clocks@idt.com

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